1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method for the same and, more specifically, to a flexible semiconductor device and a manufacturing method for the same.
2. Description of the Background Art
A recent trend, in which devices such as cellular phones have been becoming more and more compact, has enabled them to become more portable, furthermore, wearable computers have been introduced as “personal computers that you can wear”.
In addition, interfaces for directly recognizing images and speech sound such as 3DMDs (see through head mounted display), HDs with a CCD camera built in, headset type glasses and headset type microphones have also been introduced and the market for wearable devices is considered to expand in the future.
A method for converting TFT chips for AMLCDs (active matrix displays) into thin films has been proposed as one measure to meet this demand (U.S. Pat. No. 5,702,963).
According to this method, first, as shown in FIG. 4A, a substrate with an SOI structure wherein a Si buffer layer 41, a silicon oxide film 42 formed according to a CVD method, a release layer 43 made of a silicon oxide nitride film, and an upper Si layer 44 serving as an element formation layer are laminated in this order on an Si substrate 40 is used and, as shown in FIG. 4B, a pixel portion (pixel region) 44b and a TFT region 44a for an AMLCD are formed on the lamination.
Next, as shown in FIG. 4C, an oxide film 46 is formed on the pixel portion 44b and the TFT region 44a so as to form an insulator region 45.
Furthermore, as shown in FIG. 4D, a gate electrode 48 and source/drain regions 49 are formed on the substrate that has been obtained in the above-described manner and, furthermore, this is covered with an insulating film 50 and contact holes and wires 51 are formed on desired regions of the insulating film 50 so as to obtain a TFT 47.
After that, as shown in FIG. 4E, an opening 52a is formed in a release layer 43 located on the outside of the region that includes the pixel portion 44b and the TFT region 44a and, furthermore, an opening 52b that is greater than the opening 52a is formed in the silicon oxide film 42.
Subsequently, as shown in FIG. 5F, a support pillar 53 is formed of a silicon oxide film so as to fill in the openings of the silicon oxide film 42 and the release layer 43, an etchant introduction opening 54 is formed in the release layer 43 in a region other than the region that includes the pixel portion 44b and the TFT region 44a surrounded by the support pillar 53, and then an etchant is introduced from this etchant introduction opening 54 so as to remove the silicon oxide film 42 through etching as shown in FIG. 5G and to form a cavity 55. As a result, the pixel portion 44b and the TFT 47 are placed on the release layer 43 that is supported by the support pillar 53.
Next, as shown in FIG. 5H, an epoxy resin 56 and a non-photo sensitive transparent resin film 57 are formed on the entirety of the surface of the obtained substrate, and the epoxy resin 56 over the pixel portion 44b and the TFT region 44a is cured by irradiating it with ultraviolet rays while the transparent film 57 which has not been hardened is removed and the support pillar 53 is cut for cleavage, so that a chip in a thin film form is removed.
Furthermore, a method for covering the sides, or the sides and the bottom surface, of the chip with an insulating film has been proposed in addition to the above-described method (Japanese Unexamined Patent Publication No. HEI 10(1998)-223626).
According to this method, first, as shown in FIG. 6A, circuit elements (not shown) that include transistors are formed and aligned longitudinally and laterally while an insulating film 60a is formed on a semiconductor substrate 66 wherein no electrodes are formed.
Next, as shown in FIG. 6B, the bottom surface of a semiconductor substrate 66 is polished so as to reduce the thickness of the wafer to a predetermined thickness. Subsequently, as shown in FIG. 6C, trenches 62 having a cross-section in the V-form are formed longitudinally and laterally along division lines (scribe area) for dividing the circuit elements on the surface of the semiconductor substrate 66.
After that, as shown in FIG. 6D, another insulating film 60b is formed on the semiconductor substrate 66 so as to cover the surfaces of the trenches 62 and, as shown in FIG. 6E, the insulating film 60b on the surface of the semiconductor substrate 66 is selectively removed so as to expose the surface of the semiconductor substrate 66 and then an electrode is formed on the surface of the semiconductor substrate 66 and a bump is formed on this electrode so as to obtain a bump electrode (protruding electrode) 65.
Next, as shown in FIG. 6F, a tape 63 for polishing is adhered to the entire surface of the semiconductor substrate 66 by means of an adhesive 64 and, as shown in FIG. 6G, the bottom surface of the semiconductor substrate 66 is polished until the bottoms of the trenches 62 are exposed. As a result, the semiconductor substrate 66 is divided in the condition that the semiconductor substrate 66 is adhered to the tape 63 for polishing, so that semiconductor chips are formed.
Subsequently, as shown in FIG. 6H, the tape 63 for polishing and the adhesive 64 are peeled off and an insulating film 60c is formed on the bottom surface of each semiconductor chip as shown in FIG. 6I.
However, according to the methods shown in FIGS. 4A to 4E and FIGS. 5F to 5H, since an SOI substrate is used, the cost of the substrate itself is high, and the already existing technology for designing and processing semiconductor devices in bulk substrates cannot be utilized. In addition, an upper Si layer 44, which is an element formation layer, is deposited directly on the release layer 43; therefore, there is a possibility in that the upper Si layer 44 peels off during the element formation process due to a problem concerning adhesiveness between the upper Si layer 44 and the release layer 43 (adhesiveness depends on the surface form of the lower release layer), leading to a problem of a lack of flexibility due to the relative unevenness of the film thickness of the upper Si layer 44. Furthermore, the film thickness of the semiconductor layer is determined by the film thickness of the upper Si layer 44 on the SOI substrate; therefore, a problem arises wherein the film thickness cannot be freely set so that the semiconductor layer exhibits a desired flexibility and light transmission.
In addition, according to the method shown in FIGS. 6A to 6I, the insulating film that serves as a stopper exists inside of the V-form trenches; therefore, there is a possibility of causing unevenness of the film thickness or cracks in the substrate due to stress being concentrated on the bottom of the V-form trenches resulting in a lack of control when polishing the substrate. Therefore, a problem arises wherein the film thickness cannot be freely set so that the semiconductor layer exhibits a desired flexibility and light transmission.